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time_clock
- 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
clockv
- 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
Timer_basketball
- 一个用于篮球比赛30秒计时的程序，用verilog编写。可以实现alarm,reload和stop等功能。
wendukongzhiqi.rar
- 用verilog HDL语言编写的家用空调温度控制器，可实现手动，自动控制两种模式，并可实现报警功能。,Verilog HDL language used home air-conditioning temperature controller, can be achieved manually, the two modes of automatic control and alarm functions to achieve.
EDAshuzhizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and h
EDAclock
- 基于verilog的fpga电子钟设计 有时分秒显示 及闹钟功能-Based on the electric clock verilog FPGA design into four modules that sometimes the alarm clock function determined.
module_clock
- module clock alarm with asynchronous active-high reset written in verilog
max2work
- 数字钟 实现闹钟 定时校时 仿电台报时 利用verilog实现的 数电实验代码-alarm clock
alarmclock
- 用verilog hdl编写的闹钟，是fpga的应用已经经过仿真，可以正常运行-alarm clock Prepared with the verilog hdl
ANTITHEFTALARM1
- antitheft alarm in verilog
light_state_machine
- 用Verilog HDL语言写一个雷鸟车灯控制器。汽车工作状态有：空闲，左转弯，右转弯，告警。-Verilog HDL language used to write a Thunderbird lights controller. Working state vehicle are: idle, turn left, turn right, alarm.
complete
- 用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。-With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys,
alarm_machine
- basic verilog HDL samples realizing an alarm clock circuit
design-a-clk-system-by-verilogHDL
- 利用verilog语言描述的具有调时、定时、闹钟、报时等功能的时钟系统-Verilog language to describe the use of a tune, time, alarm clock, timer and other functions of the clock system
watch
- verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
deng
- HDL verilog 电子密码锁 输入错误后有报警 输入正确后有提示-HDL Verilog electronic code lock input errors have prompted alarm input is correct
clock_2
- verilog hdl 时钟程序，数码管显示，并可设置闹钟-verilog hdl clock program, the digital display, and can set the alarm
shuzizhong
- 数字钟verilog程序，实现了校时、闹钟校正、整点报时功能。-Digital clock verilog program, school, alarm clock correction, the whole point timekeeping function.
szz
- verilog HDL 硬件描述语言 FPGA 数字钟的实现 调整时间 闹钟等功能-verilog HDL hardware descr iption language implementations of FPGA digital clock adjustment time alarm clock functions
digital-clock
- verilog实现数字钟功能，闹钟功能，日历功能-Verilog digital clock function, alarm clock function, calendar function